The present invention relates generally to integrated circuits and in particular to a fuse bank structure used in integrated circuits.
An integrated circuit is a complete electronic circuit, containing transistors, diodes, resistors, and capacitors, along with their interconnecting electrical conductors, contained entirely within a single chip of silicon. Integrated circuits continue to decrease in size, and the circuits they contain continue to increase in complexity. This increases the opportunity for defective chips resulting from a failed element or a defective conductor. The complexity of these devices and the need to interconnect the circuits create very narrow performance tolerances. One way these needs have been met is to manufacture fuses into the device. Fuses can be opened to isolate defective areas and allow the rest of the circuit to be used. Fuses can also be used to trim a circuit, enable a particular mode, or enable or disable different segments of the circuit. By using fuses integrated circuit manufacturers are able to reduce the amount of semiconductor scrap. The continuous drive to reduce the overall size of integrated circuits creates a need to design fuses and other elements of integrated circuits in such a way as to minimize the space they require.
Another way to reduce semiconductor scrap is to provide redundant elements on integrated circuits. If a primary element is defective a redundant element can be substituted for that defective element. One example of an integrated circuit device which uses redundant elements is electronic memory. Typical memory circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. By providing redundant elements, defective memory cells can be replaced. Because the individual primary memory cells of a memory are separately addressable, replacing a defective cell typically comprises opening fuse-type circuits to xe2x80x98programxe2x80x99 a redundant cell to respond to the address of the defective primary cell. This process is very effective for permanently replacing defective primary memory cells.
Circuit designers continuously strive to achieve higher population capacities without a corresponding increase in physical size. Reducing the size of individual elements in integrated circuits is one way in which available die real estate is maximized. For example, as memory density increases the number of laser fuses needed for redundancy in a given memory device also increases. A 256M DRAM is expected to have more than 10,000 laser fuses. Most components of the memory devices can be scaled to meet the space restrictions resulting from the higher densities. However, laser fuses used to implement redundancy can not be scaled due to mechanical restrictions related to current laser technology. Fuse width must be kept large enough to cover the laser spot so that the fuse can absorb a large quantity of heat. In addition, the fuse-to-fuse space must be kept large enough to allow for mechanical laser alignment tolerances and to prevent unintentional programming of a fuse adjacent to an exploding fuse. These laser alignment tolerances, as well as the requirements for a large passivation opening, limit the length of the fuse. Currently the constraints dictated by the laser repair requirements limit the fuse pitch to about 3 microns. The demand for increasing numbers of fuses combined with the fixed pitch limitation create a need for improvements in the laser fuses.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a design which provides an increased density of laser fuses.
The above mentioned problems with increasing the number of fuses in a memory device are addressed by the present invention which will be understood by reading and studying the following specification. A design embodying a more efficient fuse shape is described which allows placement of more fuses in the same amount of physical space.
According to one embodiment of the present invention, an integrated circuit laser fuse system is provided, comprising a plurality of laser fuse banks. Each laser fuse bank comprises three fuses. One of the fuses is a center fuse having a narrow end, a wide end, and a common center line. Another of the fuses is a first outer fuse having a narrow end and a wide end, located adjacent to the center fuse such that the narrow end of the first outer fuse is adjacent to the narrow end of the center fuse and the wide end of the first outer fuse is adjacent to the wide end of the center fuse, the wide end of the first outer fuse is laterally offset from the narrow end of the first outer fuse. Another fuse of the fuse bank is a second outer fuse having a narrow end and a wide end, located adjacent to the center fuse and on the side of the center fuse opposite the first outer fuse such that the narrow end of the second outer fuse is adjacent to the narrow end of the center fuse and the wide end of the second outer fuse is adjacent to the wide end of the center fuse, and the wide end of the second outer fuse is laterally offset from the narrow end of the second outer fuse.
In one embodiment of the present invention the wide end of the first outer fuse is laterally offset from its narrow end in an outwardly direction away from the center fuse and the wide end of the second outer fuse is laterally offset from its narrow end in an outwardly direction away from the center fuse. In another embodiment the plurality of laser fuse banks comprise a first laser fuse bank and a second laser fuse bank positioned such that the second laser fuse bank is adjacent to the first laser fuse bank, and the second laser fuse bank is rotated one hundred eighty (180) degrees from the first laser fuse bank. In yet another embodiment the plurality of laser fuse banks are polysilicon fabricated on an integrated circuit.
According to another embodiment of the present invention the plurality of laser fuse banks are fabricated in a dynamic random access memory (DRAM). The DRAM comprises, in addition to the laser fuse banks, a plurality of primary memory cells and a plurality of redundant memory cells. The DRAM further includes a redundant enable circuit comprising a latch circuit coupled to one of the fuses of the plurality of laser fuse banks and a comparator circuit connected to the latch circuit and a plurality of external address inputs.
Yet another embodiment of the invention is an integrated circuit memory comprising an array of primary memory cells arranged in rows and columns, a plurality of redundant memory cells, and a plurality of laser fuse banks.
In yet another embodiment of the present invention, an integrated laser fuse system is provided, comprising a plurality of substantially straight laser fuses, each one of the plurality of substantially straight laser fuses being located adjacent to and parallel with remaining ones of the plurality of substantially straight laser fuses, and a common ground connection interconnecting the midpoints of the plurality of laser fuses. In yet another embodiment the plurality of laser fuse banks are polysilicon fabricated on an integrated circuit. According to another embodiment of the present invention the integrated laser fuse system is fabricated in a dynamic random access memory (DRAM) comprising the laser fuse system, a plurality of primary memory cells, a plurality of redundant memory cells, a redundant enable circuit comprising a latch circuit coupled to one of the fuses of the integrated laser fuse system, and, a comparator circuit connected to the latch circuit and a plurality of external address inputs. Another embodiment of the invention is an integrated circuit memory comprising an array of primary memory cells arranged in rows and columns, a plurality of redundant memory cells, and the integrated laser fuse system.